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TDA4841PS I2C-bus autosync deflection controller for PC monitors
Product specification Supersedes data of 1999 Oct 25 2002 Jun 24
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
FEATURES Concept features * Full horizontal plus vertical autosync capability * Extended horizontal frequency range from 15 to 130 kHz * Comprehensive set of I2C-bus driven geometry adjustments and functions, including standby mode * Very good vertical linearity * Moire cancellation * Start-up and switch-off sequence for safe operation of all power components * X-ray protection * Power dip recognition * Flexible switched mode B+ supply function block for feedback and feed forward converter * Internally stabilized voltage reference * Drive signal for focus amplifiers with combined horizontal and vertical parabola waveforms * DC controllable inputs for Extremely High Tension (EHT) compensation * SDIP32 package. Synchronization * Can handle all sync signals (horizontal, vertical, composite and sync-on-video) * Output for video clamping (leading/trailing edge selectable by I2C-bus), vertical blanking and protection blanking * Output for fast unlock status of horizontal synchronization and blanking on grid 1 of picture tube. Horizontal section * I2C-bus controllable wide range linear picture position, pin unbalance and parallelogram correction via horizontal phase * Frequency-locked loop for smooth catching of horizontal frequency * Simple frequency preset of fmin and fmax by external resistors * Low jitter * Soft start for horizontal and B+ control drive signals. Vertical section
TDA4841PS
* I2C-bus controllable vertical picture size, picture position, linearity (S-correction) and linearity balance * Output for I2C-bus controllable vertical sawtooth and parabola (for pin unbalance and parallelogram) * Vertical picture size independent of frequency * Differential current outputs for DC coupling to vertical booster * 50 to 160 Hz vertical autosync range. East-West (EW) section * I2C-bus controllable output for horizontal pincushion, horizontal size, corner and trapezium correction * Optional tracking of EW drive waveform with line frequency selectable by I2C-bus. Focus section * I2C-bus controllable output for horizontal and vertical parabolas * Vertical parabola is independent of frequency and tracks with vertical adjustments * Horizontal parabola independent of frequency * Adjustable pre-correction of delay in focus output stage.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
GENERAL DESCRIPTION The TDA4841PS is a high performance and efficient solution for autosync monitors. All functions are controllable by the I2C-bus. The TDA4841PS provides synchronization processing, horizontal and vertical synchronization with full autosync capability and very short settling times after mode changes. External power components are given a great deal of protection. The IC generates the drive waveforms for DC-coupled vertical boosters such as TDA486x and TDA835x. QUICK REFERENCE DATA SYMBOL V CC ICC ICC(stb) VSIZE VGA VPOS VLIN VLINBAL VHSIZE VHPIN VHEHT VHTRAP VHCORT VHCORB HPOS HPARAL HPINBAL Tamb supply voltage supply current supply current during standby mode vertical size VGA overscan for vertical size vertical position vertical linearity (S-correction) vertical linearity balance horizontal size voltage horizontal pincushion voltage (EW parabola) horizontal size modulation voltage horizontal trapezium correction horizontal corner correction at top of picture horizontal corner correction at bottom of picture horizontal position horizontal parallelogram EW pin unbalance ambient temperature PARAMETER MIN. 9.2 - - 60 - - -2 - 0.13 0.04 0.02 - -0.64 -0.64 - - - -20
TDA4841PS
The TDA4841PS provides extended functions e.g. as a flexible B+ control, an extensive set of geometry control facilities, and a combined output for horizontal and vertical focus signals. Together with the I2C-bus driven Philips TDA488x video processor family, a very advanced system solution is offered.
TYP. - 68 9 - 16.8 11.5 - 1.25 - - - 0.5 - - 13 1.5 1.5 -
MAX. 13.2 - - 100 - - -46 - 3.6 1.42 0.69 - +0.2 +0.2 - - - +70
UNIT V mA mA % % % % % V V V V V V % % % C
ORDERING INFORMATION TYPE NUMBER TDA4841PS PACKAGE NAME SDIP32 DESCRIPTION plastic shrink dual in-line package; 32 leads (400 mil) VERSION SOT232-1
2002 Jun 24
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2002 Jun 24
22 k (1%) VREF 23 100 nF (5%) VCAP 24 150 nF 22
BLOCK DIAGRAM
Philips Semiconductors
I2C-bus autosync deflection controller for PC monitors
EHT compensation via vertical size EHT compensation via horizontal size
7V
1.2 V
VAGC
VSMOD 21
HSMOD 31
EWDRV 11 12 13
VSYNC
(TTL level)
14
VERTICAL SYNC INPUT AND POLARITY CORRECTION
VERTICAL SYNC INTEGRATOR
VERTICAL OSCILLATOR AND AGC
EHT COMPENSATION HORIZONTAL SIZE AND VERTICAL SIZE
EW-OUTPUT
VERTICAL OUTPUT
VOUT2 VOUT1
HORIZONTAL PINCUSHION HORIZONTAL CORNER HORIZONTAL TRAPEZIUM HORIZONTAL SIZE
VERTICAL LINEARITY VERTICAL LINEARITY BALANCE
clamping blanking
CLBL
16
VIDEO CLAMPING AND VERTICAL BLANK
VERTICAL POSITION VERTICAL SIZE, VOVSCN
OUTPUT ASYMMETRIC EW-CORRECTION 20 ASCOR or
HUNLOCK
17
HUNLOCK OUTPUT
PROTECTION AND SOFT START
TDA4841PS
SDA SCL VCC
9.2 to 13.2 V 19 18 I2C-BUS RECEIVER I2C-BUS REGISTERS
FOCUS HORIZONTAL AND VERTICAL
32 FOCUS
X-RAY 6 BDRV
4
10
4 BSENS
PGND 7 SGND 25
SUPPLY AND REFERENCE
COINCIDENCE DETECTOR FREQUENCY DETECTOR
X-RAY PROTECTION
B+ CONTROL
3 BOP 5 BIN
(2) B+ CONTROL APPLICATION
HSYNC
(TTL level)
15
H/C SYNC INPUT AND POLARITY CORRECTION
PLL1 AND HORIZONTAL POSITION
HORIZONTAL OSCILLATOR
PLL2, PARALLELOGRAM, PIN UNBALANCE AND SOFT START
HORIZONTAL OUTPUT STAGE
8 HDRV
26 (video)
27
28
29
30
1
9
2
MHB603
HPLL1
HBUF
RHBUF (1) RHREF (1%)
HREF
HCAP
10 nF (2%)
HPLL2
12 nF
HFLB
XSEL
XRAY
3.3 k 100 nF
8.2 nF
TDA4841PS
Product specification
(1) For the calculation of fH range see Section "Calculation of line frequency range". (2) See Figs 25 and 26.
Fig.1 Block diagram and application circuit.
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PINNING SYMBOL HFLB XRAY BOP BSENS BIN BDRV PGND HDRV XSEL VCC EWDRV VOUT2 VOUT1 VSYNC HSYNC CLBL HUNLOCK SCL SDA ASCOR VSMOD VAGC VREF VCAP SGND HPLL1 HBUF HREF HCAP HPLL2 HSMOD FOCUS PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 horizontal flyback input X-ray protection input B+ control OTA output B+ control comparator input B+ control OTA input B+ control driver output power ground horizontal driver output select input for X-ray reset supply voltage EW waveform output vertical output 2 (ascending sawtooth) vertical output 1 (descending sawtooth) vertical synchronization input horizontal/composite synchronization input video clamping pulse/vertical blanking output horizontal synchronization unlock/protection/vertical blanking output I2C-bus clock input I2C-bus data input output for asymmetric EW corrections input for EHT compensation (via vertical size) external capacitor for vertical amplitude control external resistor for vertical oscillator external capacitor for vertical oscillator signal ground external filter for PLL1 buffered f/v voltage output reference current input for horizontal oscillator external capacitor for horizontal oscillator external filter for PLL2/soft start input for EHT compensation (via horizontal size) output for horizontal and vertical focus DESCRIPTION
TDA4841PS
2002 Jun 24
5
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Vertical sync integrator
TDA4841PS
handbook, halfpage
HFLB 1 XRAY 2 BOP 3 BSENS 4 BIN 5 BDRV 6 PGND 7 HDRV 8
32 FOCUS 31 HSMOD 30 HPLL2 29 HCAP 28 HREF 27 HBUF 26 HPLL1 25 SGND
Normalized composite sync signals from HSYNC are integrated on an internal capacitor in order to extract vertical sync pulses. The integration time is dependent on the horizontal oscillator reference current at HREF (pin 28). The integrator output directly triggers the vertical oscillator. Vertical sync slicer and polarity correction Vertical sync signals (TTL) applied to VSYNC (pin 14) are sliced at 1.4 V. The output signal of the sync slicer is integrated on an internal capacitor to detect and normalize the sync polarity. The output signals of vertical sync integrator and sync normalizer are disjuncted before they are fed to the vertical oscillator. Video clamping/vertical blanking generator The video clamping/vertical blanking signal at CLBL (pin 16) is a two-level sandcastle pulse which is especially suitable for video ICs such as the TDA488x family, but also for direct applications in video output stages. The upper level is the video clamping pulse, which is triggered by the horizontal sync pulse. Via I2C-bus control, either the leading or trailing edge can be selected by setting control bit CLAMP. The width of the video clamping pulse is determined by an internal single-shot multivibrator. The lower level of the sandcastle pulse is the vertical blanking pulse, which is derived directly from the internal oscillator waveform. It is started by the vertical sync and stopped with the start of the vertical scan. This results in optimum vertical blanking. Via I2C-bus control, two different vertical blanking times are accessible by control bit VBLK. Blanking will be activated continuously, if one of the following conditions is true: Soft start of horizontal and B+ drive (voltage at HPLL2 (pin 30) pulled down externally or by the I2C-bus) PLL1 is unlocked while frequency-locked loop is in search mode No horizontal flyback pulses at HFLB (pin 1) X-ray protection is activated Supply voltage at VCC (pin 10) is low (see Fig.22). Via I2C-bus control, horizontal unlock blanking can be switched off by control bit BLKDIS while vertical blanking is maintained.
TDA4841PS
XSEL 9 VCC 10 EWDRV 11 VOUT2 12 VOUT1 13 VSYNC 14 HSYNC 15 CLBL 16
MHB604
24 VCAP 23 VREF 22 VAGC 21 VSMOD 20 ASCOR 19 SDA 18 SCL 17 HUNLOCK
Fig.2 Pin configuration.
FUNCTIONAL DESCRIPTION Horizontal sync separator and polarity correction HSYNC (pin 15) is the input for horizontal synchronization signals, which can be DC-coupled TTL signals (horizontal or composite sync) and AC-coupled negative-going video sync signals. Video syncs are clamped to 1.28 V and sliced at 1.4 V. This results in a fixed absolute slicing level of 120 mV related to sync top. For DC-coupled TTL signals the input clamping current is limited. The slicing level for TTL signals is 1.4 V. The separated sync signal (either video or TTL) is integrated on an internal capacitor to detect and normalize the sync polarity. Normalized horizontal sync pulses are used as input signals for the vertical sync integrator, the PLL1 phase detector and the frequency-locked loop. 2002 Jun 24 6
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Frequency-locked loop The frequency-locked loop can lock the horizontal oscillator over a wide frequency range. This is achieved by a combined search and PLL operation. The frequency range is preset by two external resistors and the f max recommended maximum ratio is --------- = 6.5 f min This can, for instance, be a range from 15.625 to 90 kHz with all tolerances included. Without a horizontal sync signal the oscillator will be free-running at fmin. Any change of sync conditions is detected by the internal coincidence detector. A deviation of more than 4% between horizontal sync and oscillator frequency will switch the horizontal section into search mode. This means that PLL1 control currents are switched off immediately. The internal frequency detector then starts tuning the oscillator. Very small DC currents at HPLL1 (pin 26) are used to perform this tuning with a well defined change rate. When coincidence between horizontal sync and oscillator frequency is detected, the search mode is first replaced by a soft-lock mode which lasts for the first part of the next vertical period. The soft-lock mode is then replaced by a normal PLL operation. This operation ensures a smooth tuning and avoids fast changes of horizontal frequency during catching. In this concept it is not allowed to load HPLL1. The frequency dependent voltage at this pin is fed internally to HBUF (pin 27) via a sample-and-hold and buffer stage. The sample-and-hold stage removes all disturbances caused by horizontal sync or composite vertical sync from the buffered voltage. An external resistor connected between pins HBUF and HREF defines the frequency range. Out-of-lock indication (pin HUNLOCK) Pin HUNLOCK is floating during search mode or if a protection condition is true. All this can be detected by the microcontroller if a pull-up resistor is connected to its own supply voltage. For an additional fast vertical blanking at grid 1 of the picture tube, a 1 V signal referenced to ground is available at this output. Also the continuous protection blanking (see Section "Video clamping/vertical blanking generator") is available at this pin. Via I2C-bus control, the control bit BLKDIS can switch off horizontal unlock blanking while vertical blanking is maintained. Horizontal oscillator
TDA4841PS
The horizontal oscillator is of the relaxation type and requires a capacitor of 10 nF at HCAP (pin 29). For optimum jitter performance the value of 10 nF must not be changed. The minimum oscillator frequency is determined by a resistor connected between pin HREF and ground. A resistor connected between pins HREF and HBUF defines the frequency range. The reference current at pin HREF also defines the integration time constant of the vertical sync integration. Calculation of line frequency range First the oscillator frequencies fmin and fmax have to be calculated. This is achieved by adding the spread of the relevant components to the highest and lowest sync frequencies fsync(min) and fsync(max). The oscillator is driven by the currents in RHREF and RHBUF. Table 1 describes a 31.45 to 90 kHz application. Table 1 Calculation of total spread for fmax 3% 2% 2% 7% for fmin 5% 2% 2% 9%
spread of IC CHCAP RHREF, RHBUF Total
Thus the typical frequency range of the oscillator in this example is: f max = f sync ( max ) x 1.07 = 96.3 kHz f sync ( min f min = ----------------------) = 28.4 kHz 1.09 The resistors RHREF and RHBUFpar can be calculated with the following formulae: 78 x kHz x k R HREF = ----------------------------------------------------------------- = 2.61 k 2 f min + 0.0012 x f min [ kHz ] 78 x kHz x k R HBUFpar = ------------------------------------------------------------------- = 726 2 f max + 0.0012 x f max [ kHz ] The resistor RHBUFpar is calculated as the value of RHREF and RHBUF in parallel.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
The formulae for RHBUF additionally takes into account the voltage swing across this resistor: R HREF x R HBUFpar R HBUF = --------------------------------------------- x 0.8 = 805 R HREF - R HBUFpar PLL1 phase detector The phase detector is a standard type using switched current sources, which are independent of the horizontal frequency. It compares the middle of horizontal sync with a fixed point on the oscillator sawtooth voltage. The PLL1 loop filter is connected to HPLL1 (pin 26). See also Section "Horizontal position adjustment and corrections". Horizontal position adjustment and corrections Via register HPOS the I2C-bus allows a linear adjustment of the relative phase between the horizontal sync and oscillator sawtooth (in PLL1 loop). Once adjusted, the relative phase remains constant over the whole frequency range. Via registers HPARAL and HPINBAL correction of pin unbalance and parallelogram is achieved by modulating the phase between oscillator sawtooth and horizontal flyback (in loop PLL2). If those asymmetric EW corrections are performed in the deflection stage, both registers can be disconnected from horizontal phase via control bit ACD. This does not change the output at pin ASCOR. Horizontal moire cancellation To achieve a cancellation of horizontal moire (also known as `video moire'), the horizontal frequency is divided-by-two for a modulation of the horizontal phase via PLL2. The amplitude is controlled by register HMOIRE. To avoid a visible structure on screen the polarity changes with half the vertical frequency. Control bit MOD disables the moire cancellation function. PLL2 phase detector The PLL2 phase detector is similar to the PLL1 detector and compares the line flyback pulse at HFLB (pin 1) with the oscillator sawtooth voltage. The control currents are independent of the horizontal frequency. The PLL2 detector thus compensates for the delay in the external horizontal deflection circuit by adjusting the phase of the HDRV (pin 8) output pulse. An external modulation of the PLL2 phase is not allowed, because this would disturb the pre-correction of the H-focus parabola. Soft start and standby
TDA4841PS
If HPLL2 is pulled to ground, either by an external DC current or by resetting the register SOFTST, horizontal output pulses and B+ control driver pulses are inhibited. This means that HDRV (pin 8), BDRV (pin 6), VOUT1 (pin 13) and VOUT2 (pin 12) are floating in this state. PLL2 and the frequency-locked loop are disabled, CLBL (pin 16) provides a continuous blanking signal and HUNLOCK (pin 17) is floating. This option can be used for soft start, protection and power-down modes. When the HPLL2 pin is released again, an automatic soft start sequence on the horizontal drive as well as on the B- drive output will be performed (see Fig.22). A soft start can only be performed if the supply voltage for the IC is 8.6 V at minimum. The soft start timing is determined by the filter capacitor at HPLL2 (pin 30), which is charged with an constant current during soft start. If the voltage at pin 30 (HPLL2) reaches 1.1 V, the vertical output currents are enabled. At 1.8 V the horizontal driver stage generates very small output pulses. The width of these pulses increases with the voltage at HPLL2 until the final duty cycle is reached. The voltage at HPLL2 increases further and performs a soft start at BDRV (pin 6) as well. After BDRV has reached full duty cycle, the voltage at HPLL2 continues to rise until HPLL2 enters its normal operating range. The internal charge current is now disabled. Finally PLL2 and the frequency-locked loop are activated. If both functions reach normal operation, HUNLOCK (pin 17) switches from the floating status to normal vertical blanking, and continuous blanking at CLBL (pin 16) is removed. Output stage for line drive pulses [HDRV (pin 8)] An open-collector output stage allows direct drive of an inverting driver transistor because of a low saturation voltage of 0.3 V at 20 mA. To protect the line deflection transistor, the output stage is disabled (floating) for low supply voltage at VCC (see Fig.26). The duty cycle of line drive pulses is slightly dependent on the actual horizontal frequency. This ensures optimum drive conditions over the whole frequency range.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
X-ray protection The X-ray protection input XRAY (pin 2) provides a voltage detector with a precise threshold. If the input voltage at XRAY exceeds this threshold for a certain period of time, control bit SOFTST is reset, which switches the IC into protection mode. In this mode several pins are forced into defined states: HUNLOCK (pin 17) is floating The capacitor connected to HPLL2 (pin 30) is discharged Horizontal output stage (HDRV) is floating B+ control driver stage (BDRV) is floating Vertical output stages (VOUT1 and VOUT2) are floating CLBL provides a continuous blanking signal. There are two different ways to restart the IC: 1. XSEL (pin 9) is open-circuit or connected to ground. The control bit SOFTST must be set to logic 1 via the I2C-bus. The IC then returns to normal operation via soft start. 2. XSEL is connected to VCC via an external resistor. The supply voltage of the IC must be switched off for a certain time before the IC can be restarted again using the standard power-on procedure. Vertical oscillator and amplitude control This stage is designed for fast stabilization of vertical size after changes in sync frequency conditions. The free-running frequency ffr(V) is determined by the resistor RVREF connected to pin 23 and the capacitor CVCAP connected to pin 24. The value of RVREF is not only optimized for noise and linearity performance in the whole vertical and EW section, but also influences several internal references. Therefore the value of RVREF must not be changed. Capacitor CVCAP should be used to select the free-running frequency of the vertical oscillator in accordance with the following formula: 1 f fr(V) = ---------------------------------------------------------10.8 x R VREF x C VCAP To achieve a stabilized amplitude the free-running frequency ffr(V), without adjustment, should be at least 10% lower than the minimum trigger frequency. The contributions shown in Table 2 can be assumed. Table 2
TDA4841PS
Calculation of ffr(V) total spread Contributing elements
Minimum frequency offset between ffr(V) and lowest trigger frequency Spread of IC Spread of RVREF Spread of CVCAP Total Result for 50 to 160 Hz application: 50 Hz f fr(V) = -------------- = 42 Hz 1.19
10% 3% 1% 5% 19%
The AGC of the vertical oscillator can be disabled by setting control bit AGCDIS via the I2C-bus. A precise external current has to be injected into VCAP (pin 24) to obtain the correct vertical size. This special application mode can be used when the vertical sync pulses are serrated (shifted); this condition is found in some display modes, e.g. when using a 100 Hz upconverter for video signals. Application hint: VAGC (pin 22) has a high input impedance during scan. Therefore, the pin must not be loaded externally; otherwise non-linearities in the vertical output currents may occur due to the changing charge current during scan. Adjustment of vertical size, VGA overscan and EHT compensation There are four different ways to adjust the amplitude of the differential output currents at VOUT1 and VOUT2: 1. Register VGAIN changes the vertical size without affecting any other output signal of the IC; this adjustment is meant for factory alignments. 2. Register VSIZE changes not only the vertical size, but also provides the correct tracking of all other related waveforms (see Section "Tracking of vertical adjustments"); this register should be used for user adjustments. 3. For the VGA350 mode the register VOVSCN can activate a +17% step in vertical size. 4. VSMOD (pin 21) can be used for a DC controlled EHT compensation of vertical size by correcting the differential output currents at VOUT1 and VOUT2; VSMOD does not affect the EW waveforms, vertical focus, pin unbalance and parallelogram corrections.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Adjustment of vertical position, vertical linearity and vertical linearity balance Register VOFFS provides a DC shift at the sawtooth output VOUT1 and VOUT2 (pins 13 and 12) without affecting any other output waveform. This adjustment is meant for factory alignments. Register VPOS provides a DC shift at the sawtooth output VOUT1 and VOUT2 with correct tracking of all other related waveforms (see Section "Tracking of vertical adjustments"). This register should be used for user adjustments. Due to the tracking the whole picture moves vertically while maintaining the correct geometry. Register VLIN is used to adjust the amount of vertical S-correction in the output signal. This function can be switched off by control bit VSC. Register VLINBAL is used to correct the unbalance of vertical S-correction in the output signal. Tracking of vertical adjustments The adjustments via registers VSIZE, VOVSCN and VPOS also affect the waveforms of horizontal pincushion, vertical linearity (S-correction), vertical linearity balance, focus parabola, pin unbalance and parallelogram correction. The result of this interaction is that no readjustment of these parameters is necessary after an user adjustment of vertical picture size and vertical picture position. Adjustment of vertical moire cancellation To achieve a cancellation of vertical moire (also known as `scan moire') the vertical picture position can be modulated by half the vertical frequency. The amplitude of the modulation is controlled by register VMOIRE and can be switched off via control bit MOD. Horizontal pincushion (including horizontal size, corner correction and trapezium correction) EWDRV (pin 11) provides a complete EW drive waveform. The components horizontal pincushion, horizontal size, corner correction and trapezium correction are controlled by the registers HPIN, HSIZE, HCORT, HCORB and HTRAP. The corner correction can be adjusted separately for the top (HCORT) and bottom (HCORB) part of the picture. The pincushion (EW parabola) amplitude, corner and trapezium correction track with vertical picture size (VSIZE) and also with the adjustment for vertical picture
TDA4841PS
position (VPOS). The corner correction does not track with horizontal pincushion (HPIN). Further the horizontal pincushion amplitude, corner and trapezium correction track with the horizontal picture size, which is adjusted via register HSIZE and the analog modulation input HSMOD. If the DC component in the EWDRV output signal is increased via HSIZE or IHSMOD, the pincushion, corner and trapezium component of the EWDRV output will be reduced by a factor of V HSIZE V HSIZE + V HEHT 1 - ---------------- 14.4 V 1 - -----------------------------------------------------------------------14.4 V The value 14.4 V is a virtual voltage for calculation only. The output pin can not reach this value, but the gain (and DC bias) of the external application should be such that the horizontal deflection is reduced to zero when EWDRV would reach 14.4 V. HSMOD (pin 31) can be used for a DC controlled EHT compensation by correcting horizontal size, horizontal pincushion, corner and trapezium. The control range at this pin tracks with the actual value of HSIZE. For an increasing DC component VHSIZE in the EWDRV output signal, the DC component VHEHT caused by IHSMOD will be V HSIZE reduced by a factor of 1 - ---------------- as shown in the equation 14.4 V above. The whole EWDRV voltage is calculated as follows: V EWDRV,0 = 1.2 V + [ V HSIZE + V HEHT x f(HSIZE) + ( V HPIN + V HCOR + V HTRAP ) x g(HSIZE,HSMOD) ] x h(I HREF) where: I HSMOD V HEHT = ------------------- x 0.69 120 A V HSIZE f(HSIZE) = 1 - ---------------14.4 V V HSIZE V HSIZE + V HEHT 1 - ---------------- 14.4 V g(HSIZE,HSMOD) = 1 - -----------------------------------------------------------------------14.4 V I HREF h(I HREF) = ----------------------------------------I HREF at f = 70 kHz
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Via control bit FHMULT two different modes of operation can be chosen for the EW output waveform: 1. Mode 1 Horizontal size is controlled via register HSIZE and causes a DC shift at the EWDRV output. The complete waveform is also multiplied internally by a signal proportional to the line frequency [which is detected via the current at HREF (pin 28)]. This mode is to be used for driving EW diode modulator stages which require a voltage proportional to the line frequency. 2. Mode 2 The EW drive waveform does not track with the line frequency. This mode is to be used for driving EW modulators which require a voltage independent of the line frequency. Output stage for asymmetric correction waveforms [ASCOR (pin 20)] This output is designed as a voltage output for superimposed waveforms of vertical parabola and sawtooth. Via the I2C-bus the registers HPARAL and HPINBAL allow to change amplitude and polarity of both signals. Application hint: The TDA4841PS offers two possibilities to control HPINBAL and HPARAL. 1. Control bit ACD = 1. The two registers now control the horizontal phase by means of internal modulation of the PLL2 horizontal phase control. The ASCOR output (pin 20) can be left unused, but it will always provide an output signal because the ASCOR output stage is not influenced by the control bit ACD. 2. Control bit ACD = 0. The internal modulation via PLL2 is disconnected. In order to obtain the required effect on the screen, pin ASCOR must now be fed to the DC amplifier which controls the DC shift of the horizontal deflection. This option is useful for applications which already use a DC shift transformer. If the tube does not need HPINBAL and HPARAL, then pin ASCOR can be used for other purposes, i.e. for a simple dynamic convergence.
TDA4841PS
Dynamic focus section [FOCUS (pin 32)] This section generates a complete drive signal for dynamic focus applications. The amplitude of the horizontal parabola is internally stabilized, thus it is independent of the horizontal frequency. The amplitude can be adjusted via register HFOCUS. Changing horizontal size may require a correction of HFOCUS. To compensate for the delay in external focus amplifiers a `pre-correction' for the phase of the horizontal parabola has been implemented (see Fig.28). The amount of this pre-correction can be adjusted via register HFOCAD. The amplitude of the vertical parabola is independent of frequency and tracks with all vertical adjustments. The amplitude can be adjusted via register VFOCUS. FOCUS (pin 32) is designed as a voltage output for the superimposed vertical and horizontal parabolas. B+ control function block The B+ control function block of the TDA4841PS consists of an Operational Transconductance Amplifier (OTA), a voltage comparator, a flip-flop and a discharge circuit (see Fig.25). This configuration allows easy applications for different B+ control concepts. See also Application Note AN96052: "B+ converter Topologies for Horizontal Deflection and EHT with TDA4855/58". GENERAL DESCRIPTION The non-inverting input of the OTA is connected internally to a high precision reference voltage. The inverting input is connected to BIN (pin 5). An internal clamping circuit limits the maximum positive output voltage of the OTA. The output itself is connected to BOP (pin 3) and to the inverting input of the voltage comparator. The non-inverting input of the voltage comparator can be accessed via BSENS (pin 4). B+ drive pulses are generated by an internal flip-flop and fed to BDRV (pin 6) via an open-collector output stage. This flip-flop will be set at the rising edge of the signal at HDRV (pin 8). The falling edge of the output signal at BDRV has a defined delay of td(BDRV) to the rising edge of the HDRV pulse. When the voltage at BSENS exceeds the voltage at BOP, the voltage comparator output resets the flip-flop and, therefore, the open-collector stage at BDRV is floating again.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
An internal discharge circuit allows a well defined discharge of capacitors at BSENS. BDRV is active at a LOW-level output voltage (see Figs 25 and 26), thus it requires an external inverting driver stage. The B+ function block can be used for B+ deflection modulators in many different ways. Two popular application combinations are: * Boost converter in feedback mode (see Fig.25) In this application the OTA is used as an error amplifier with a limited output voltage range. The flip-flop will be set at the rising edge of the signal at HDRV. A reset will be generated when the voltage at BSENS, taken from the current sense resistor, exceeds the voltage at BOP. If no reset is generated within a line period, the rising edge of the next HDRV pulse forces the flip-flop to reset. The flip-flop is set immediately after the voltage at BSENS has dropped below the threshold voltage VRESTART(BSENS). * Buck converter in feed forward mode (see Fig.26) This application uses an external RC combination at BSENS to provide a pulse width which is independent from the horizontal frequency. The capacitor is charged via an external resistor and discharged by the internal discharge circuit. For normal operation the discharge circuit is activated when the flip-flop is reset by the internal voltage comparator. The capacitor will now be discharged with a constant current until the internally controlled stop level VSTOP(BSENS) is reached. This level will be maintained until the rising edge of the next HDRV pulse sets the flip-flop again and disables the discharge circuit. If no reset is generated within a line period, the rising edge of the next HDRV pulse automatically starts the discharge sequence and resets the flip-flop. When the voltage at BSENS reaches the threshold voltage VRESTART(BSENS), the discharge circuit will be disabled automatically and the flip-flop will be set immediately. This behaviour allows a definition of the maximum duty cycle of the B+ control drive pulse by the relationship of charge current to discharge current.
TDA4841PS
Supply voltage stabilizer, references, start-up procedures and protection functions The TDA4841PS provides an internal supply voltage stabilizer for excellent stabilization of all internal references. An internal gap reference, especially designed for low-noise, is the reference for the internal horizontal and vertical supply voltages. All internal reference currents and drive current for the vertical output stage are derived from this voltage via external resistors. If either the supply voltage is below 8.3 V or no data from the I2C-bus has been received after power-up, the internal soft start and protection functions do not allow any of those outputs [HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK (see Fig.22)] to be active. For supply voltages below 8.3 V the internal I2C-bus will not generate an acknowledge and the IC is in standby mode. This is because the internal protection circuit has generated a reset signal for the soft start register SOFTST. Above 8.3 V data is accepted and all registers can be loaded. If the SOFTST register has received a set from the I2C-bus, the internal soft start procedure is released, which activates all outputs which are mentioned above. If during normal operation the supply voltage has dropped below 8.1 V, the protection mode is activated and HUNLOCK (pin 17) changes to the protection status and is floating. This can be detected by the microprocessor. This protection mode has been implemented in order to protect the deflection stages and the picture tube during start-up, shut-down and fault conditions. This protection mode can be activated as shown in Table 3.
2002 Jun 24
12
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Table 3 Activation of protection mode ACTIVATION Low supply voltage at pin 10 Power dip, below 8.1 V RESET increase supply voltage, reload registers, soft start via I2C-bus reload registers, soft start via I2C-bus or via supply voltage reload registers, soft start via I2C-bus release pin 30 Power dip recognition
TDA4841PS
In standby mode the I2C-bus will only answer with an acknowledge when data is sent to the control register 1AH. This register contains the standby and soft start control bit. If the I2C-bus master transmits data to another register, an acknowledge is given after the chip address and the subaddress; an acknowledge is not given after the data. This indicates that data can be stored into normal registers only in soft start mode. If the supply voltage drops below 8.1 V the deflection controller leaves normal operation and changes to standby mode. The microcontroller can check this state by sending data into a register with the subaddress 0XH. The acknowledge will only be given on the data if the IC is active. Due to this behaviour the start-up of the TDA4841PS is defined as follows: the first data that is transferred to the deflection controller must be sent to the control register with subaddress 1AH. Any other subaddress will not lead to an acknowledge. This is a limitation in checking the I2C-busses of the monitor during start-up.
X-ray protection XRAY (pin 2) triggered HPLL2 (pin 30) externally pulled to ground
When the protection mode is active, several pins of the TDA4841PS are forced into a defined state: HDRV (horizontal driver output) is floating BDRV (B+ control driver output) is floating HUNLOCK (indicates, that the frequency-to-voltage converter is out of lock) is floating (HIGH via external pull-up resistor) CLBL provides a continuous blanking signal VOUT1 and VOUT2 (vertical outputs) are floating The capacitor at HPLL2 is discharged. If the soft start procedure is activated via the I2C-bus, all of these actions will be performed in a well defined sequence (see Figs 22 and 23).
2002 Jun 24
13
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 60134); all voltages measured with respect to ground. SYMBOL VCC Vi(n) supply voltage input voltage pin BIN pins HSYNC, VSYNC, VREF, HREF, VSMOD and HSMOD pins SDA, SCL and XRAY Vo(n) output voltage pins VOUT2, VOUT1 and HUNLOCK pins BDRV and HDRV VI/O(n) Io(HDRV) Ii(HFLB) Io(CLBL) Io(BOP) Io(BDRV) Io(EWDRV) Vo(EWDRV) Io(FOCUS) Tamb Tj Tstg Vesd input/output voltages at pins BOP and BSENS horizontal driver output current horizontal flyback input current video clamping pulse/vertical blanking output current B+ control OTA output current B+ control driver output current EW driver output current maximum EW driver output voltage focus driver output current ambient temperature junction temperature storage temperature electrostatic discharge voltage for all pins note 1 note 2 Notes 1. Machine model: 200 pF; 0.75 H; 10 . 2. Human body model: 100 pF; 7.5 H; 1500 . THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 55 UNIT K/W -0.5 -0.5 -0.5 - -10 - - - - -0.5 - -20 - -55 -150 -2000 +6.5 +13.2 +6.0 100 +10 -10 1 50 -5 VCC -5 +70 150 +150 +150 +2000 V V V mA mA mA mA mA mA V mA C C C V V -0.5 -0.5 -0.5 +6.0 +6.5 +8.0 V V V PARAMETER CONDITIONS MIN. -0.5 MAX. +13.2 V UNIT
QUALITY SPECIFICATION In accordance with "URF-4-2-59/601"; EMC emission/immunity test in accordance with "DIS 1000 4.6" (IEC 801.6). SYMBOL VEMC emission test immunity test Note 1. Tests are performed with application reference board. Tests with other boards will have different results. 2002 Jun 24 14 PARAMETER CONDITIONS note 1 note 1 MIN. - - TYP. 1.5 2.0 MAX. - - UNIT mV V
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
CHARACTERISTICS VCC = 12 V; Tamb = 25 C; peripheral components in accordance with Fig.1; unless otherwise specified. SYMBOL Horizontal sync separator INPUT CHARACTERISTICS FOR DC-COUPLED TTL SIGNALS: PIN HSYNC Vi(HSYNC) VHSYNC(sl) tr(HSYNC) tf(HSYNC) tW(HSYNC)(min) Ii(HSYNC) sync input signal voltage slicing voltage level rise time of sync pulse fall time of sync pulse minimum width of sync pulse input current Vi(HSYNC) = 0.8 V Vi(HSYNC) = 5.5 V VHSYNC VHSYNC(AC,sl) Vclamp(HSYNC) Ich(HSYNC) tW(HSYNC)(min) Rsource(max) Ri(diff)(HSYNC) sync amplitude of video input signal voltage slicing voltage level (measured from top sync) charge current for coupling capacitor minimum width of sync pulse maximum source resistance differential input resistance duty cycle = 7% during sync Rsource = 50 Rsource = 50 1.7 1.2 10 10 0.7 - - - 90 1.1 1.7 0.7 - - - - 1.4 - - - - - 300 120 1.28 2.4 - - 80 - - 20 10 5.7 3.8 - 1.6 500 500 - -200 10 - 150 1.5 3.4 - 1500 - 25 V V ns ns s A A mV mV V A s % PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUT CHARACTERISTICS FOR AC-COUPLED VIDEO SIGNALS (SYNC-ON-VIDEO, NEGATIVE SYNC POLARITY)
top sync clamping voltage level Rsource = 50 Vi(HSYNC) > Vclamp(HSYNC)
Automatic polarity correction for horizontal sync t P(H) ---------tH td(HPOL) tint(V) horizontal sync pulse width related to tH delay time for changing polarity
0.3
1.8
ms s s s s
Vertical sync integrator integration time for generation of a vertical trigger pulse fH = 15.625 kHz; IHREF = 0.52 mA fH = 31.45 kHz; IHREF = 1.052 mA fH = 64 kHz; IHREF = 2.141 mA fH = 100 kHz; IHREF = 3.345 mA Vertical sync slicer (DC-coupled, TTL compatible): pin VSYNC Vi(VSYNC) VVSYNC(sl) Ii(VSYNC) sync input signal voltage slicing voltage level input current 0 V < Vi(VSYNC) < 5.5 V 1.7 1.2 - - 1.4 - - 1.6 10 V V A 14 7 3.9 2.5 26 13 6.5 4.5
2002 Jun 24
15
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS - 0.45 MIN. - - 0.7 4.75 4 50 130
TDA4841PS
TYP.
MAX.
UNIT s ms s V mV/K ns/V ns
Automatic polarity correction for vertical sync tVSYNC(max) td(VPOL) tclamp(CLBL) Vclamp(CLBL) TCclamp STPSclamp td(HSYNCt-CLBL) maximum width of vertical sync pulse delay time for changing polarity 400 1.8
Video clamping/vertical blanking output: pin CLBL width of video clamping pulse top voltage level of video clamping pulse temperature coefficient of Vclamp(CLBL) steepness of slopes for clamping pulse delay between trailing edge of horizontal sync and start of video clamping pulse maximum duration of video clamping pulse referenced to end of horizontal sync delay between leading edge of horizontal sync and start of video clamping pulse maximum duration of video clamping pulse referenced to end of horizontal sync top voltage level of vertical blanking pulse width of vertical blanking pulse at pins CLBL and HUNLOCK temperature coefficient of Vblank(CLBL) output voltage during vertical scan temperature coefficient of Vscan(CLBL) internal sink current external load current ICLBL = 0 RL = 1 M; CL = 20 pF clamping pulse triggered on trailing edge of horizontal sync; control bit CLAMP = 0; measured at VCLBL = 3 V clamping pulse triggered on leading edge of horizontal sync; control bit CLAMP = 1; measured at VCLBL = 3 V notes 1 and 2 control bit VBLK = 0 control bit VBLK = 1 measured at VCLBL = 3 V 0.6 4.32 - - - 0.8 5.23 - - -
tclamp(max)
-
-
1.0
s
td(HSYNCl-CLBL)
-
300
-
ns
tclamp(max)
-
-
0.15
s
Vblank(CLBL) tblank(CLBL) TCblank Vscan(CLBL) TCscan Isink(CLBL) IL(CLBL)
1.7 220 305 - 0.59 - 2.4 -
1.9 260 350 2 0.63 -2 - -
2.1 300 395 - 0.67 - - -3.0
V s s mV/K V mV/K mA mA
2002 Jun 24
16
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS RHBUF = ; RHREF = 2.4 k; CHCAP = 10 nF; note 3 MIN.
TDA4841PS
TYP.
MAX.
UNIT
Horizontal oscillator: pins HCAP and HREF ffr(H) free-running frequency without PLL1 action (for testing only) spread of free-running frequency (excluding spread of external components) temperature coefficient of free-running frequency maximum oscillator frequency voltage at input for reference current 30.53 31.45 32.39 kHz
ffr(H)
-
-
3.0
%
TCfr fH(max) VHREF
-100 - 2.43
0 - 2.55
+100 130 2.68
10-6/K kHz V
Unlock blanking detection: pin HUNLOCK Vscan(HUNLOCK) low-level voltage of HUNLOCK saturation voltage in case of locked PLL1; internal sink current = 1 mA IL = 0 - - 250 mV
Vblank(HUNLOCK) TCblank TCsink Isink(int) IL(max) ILI
blanking level of HUNLOCK temperature coefficient of Vblank(HUNLOCK) temperature coefficient of Isink(HUNLOCK) internal sink current maximum external load current leakage current
0.9 - -
1 -0.9 0.15 2.0 - -
1.1 - - 2.6 -2 5
V mV/K %/K mA mA A
for blanking pulses; PLL1 locked VHUNLOCK = 1 V VHUNLOCK = 5 V in case of unlocked PLL1 and/or protection active
1.4 - -
PLL1 phase comparator and frequency-locked loop: pins HPLL1 and HBUF tW(HSYNC)(max) maximum width of horizontal sync pulse (referenced to line period) total lock-in time of PLL1 control currents notes 4 and 5 locked mode; level 1 locked mode; level 2 VHBUF buffered f/v voltage at HBUF (pin 27) minimum horizontal frequency maximum horizontal frequency - - - - 15 145 2.55 0.5 - - - - A A V V - - 25 %
tlock(HPLL1) Ictrl(HPLL1)
-
40
80
ms
2002 Jun 24
17
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS - - - - - - - - - - - - 36 MIN.
TDA4841PS
TYP. -13 0 13 -1.2 1.2 0.02 -1.2 1.2 0.02 0 0.02
MAX. - - - - - - - - - - - - -
UNIT
Phase adjustments and corrections via PLL1 and PLL2 HPOS horizontal position (referenced to horizontal period) register HPOS = 0 register HPOS = 127 register HPOS = 255 HPINBAL horizontal pin unbalance correction via HPLL2 (referenced to horizontal period) register HPINBAL = 0; note 6 register HPINBAL = 63; note 6 register HPINBAL = 32; note 6 HPARAL horizontal parallelogram correction (referenced to horizontal period) register HPARAL = 0; note 6 register HPARAL = 63; note 6 register HPARAL = 32; note 6 HMOIRE relative modulation of horizontal position by 1 horizontal frequency; 2 phase alternates with 1 vertical frequency 2 moire cancellation off PLL2 phase detector: pins HFLB and HPLL2 PLL2 PLL2 control (advance of horizontal drive with respect to middle of horizontal flyback) maximum advance; register HPINBAL = 32; register HPARAL = 32 - % register HMOIRE = 0; control bit MOD = 0 register HMOIRE = 63; control bit MOD = 0 control bit MOD = 1 % % % % % % % % % % %
0
%
minimum advance; register - HPINBAL = 32; register HPARAL = 32 Ictrl(PLL2) PLL2 PLL2 control current relative sensitivity of PLL2 phase shift related to horizontal period maximum voltage for PLL2 protection mode/soft start charge current for external capacitor during soft start discharge current for external capacitor during soft down VHPLL2 < 3.7 V VHPLL2 < 3.7 V - -
7
-
%
75 28
- -
A mV/%
VPROT(HPLL2)(max) Ich(PLL2) Idch(PLL2)
- - -
4.6 1 -1
- - -
V A A
2002 Jun 24
18
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS - - - - - MIN.
TDA4841PS
TYP.
MAX. - - 6 -2 -
UNIT
HORIZONTAL FLYBACK INPUT: PIN HFLB Vpos(HFLB) Vneg(HFLB) Ipos(HFLB) Ineg(HFLB) Vsl(HFLB) positive clamping level negative clamping level positive clamping current negative clamping current slicing level Ii(HFLB) = 5 mA Ii(HFLB) = -1 mA 5.5 -0.75 - - 2.8 V V mA mA V
Output stage for line driver pulses: pin HDRV OPEN-COLLECTOR OUTPUT STAGE Vsat(HDRV) ILO(HDRV) tHDRV(OFF)/tH saturation voltage output leakage current Io(HDRV) = 20 mA Io(HDRV) = 60 mA VHDRV = 16 V Io(HDRV) = 20 mA; fH = 31.45 kHz; see Fig.16 Io(HDRV) = 20 mA; fH = 58 kHz; see Fig.16 Io(HDRV) = 20 mA; fH = 110 kHz; see Fig.16 AUTOMATIC VARIATION OF DUTY CYCLE relative tOFF time of HDRV output; measured at VHDRV = 3 V; HDRV duty cycle is modulated by the relation IHREF/IVREF 42 45.5 49 45 48.5 52 48 51.5 55 % % % - - - - - - 0.3 0.8 10 V V A
X-ray protection: pin XRAY VXRAY(sl) tW(XRAY)(min) Ri(XRAY) slicing voltage level for latch minimum width of trigger pulse input resistance at XRAY (pin 2) VXRAY < 6.38 V + VBE VXRAY > 6.38 V + VBE standby mode XRAYrst reset of X-ray latch pin 9 open-circuit or connected to GND pin 9 connected to VCC via RXSEL VCC(XRAY)(min) minimum supply voltage for correct function of the X-ray latch maximum supply voltage for reset of the X-ray latch external resistor at pin 9 pin 9 connected to VCC via RXSEL pin 9 connected to VCC via RXSEL no reset via I2C-bus 6.22 - 500 - - 6.39 - - 5 5 6.56 30 - - - V s k k k
set control bit SOFTST via I2C-bus switch off VCC, then re-apply VCC - - 4 V
VCC(XRAY)(max) RXSEL
2 56
- -
- 130
V k
2002 Jun 24
19
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS MIN.
TDA4841PS
TYP.
MAX.
UNIT
Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency ffr(V)) ffr(V) fcr(V) VVREF td(scan) free-running frequency vertical frequency catching range voltage at reference input for vertical oscillator delay between trigger pulse and start of ramp at VCAP (pin 24) (width of vertical blanking pulse) amplitude control current external capacitor at VAGC (pin 22) control bit VBLK = 0 control bit VBLK = 1 RVREF = 22 k; CVCAP = 100 nF constant amplitude; note 7 40 50 - 220 305 42 - 3.0 260 350 43.3 160 - 300 395 Hz Hz V s s A A nF
IVAGC CVAGC
control bit AGCDIS = 0 control bit AGCDIS = 1
120 - 150
200 0 -
300 - 220
Differential vertical current outputs ADJUSTMENT OF VERTICAL SIZE INCLUDING VGA AND EHT COMPENSATION; see Figs 3 to 7 VGAIN vertical size without VGA overscan (referenced to nominal vertical size) register VGAIN = 0; register VSIZE = 127; bit VOVSCN = 0; note 8 register VGAIN = 63; register VSIZE = 127; bit VOVSCN = 0; note 8 VSIZE vertical size without VGA overscan (referenced to nominal vertical size) register VSIZE = 0; register VGAIN = 63; bit VOVSCN = 0; note 8 register VSIZE = 127; register VGAIN = 63; bit VOVSCN = 0; note 8 VSIZEVGA vertical size with VGA overscan register VSIZE = 0; (referenced to nominal vertical register VGAIN = 63; size) bit VOVSCN = 1; note 8 register VSIZE = 127; register VGAIN = 63; bit VOVSCN = 1; note 8 VSMOD EHT compensation on vertical size via VSMOD (pin 21) (referenced to 100% vertical size) input current (pin 21) input resistance reference voltage at input Ii(VSMOD) = 0 Ii(VSMOD) = -120 A - 70 - %
-
100
-
%
-
60
-
%
-
100
-
%
-
70
-
%
115.9
116.8
117.7
%
- - - - 300 -
0 -7
- - - - 500 -
% %
Ii(VSMOD) Ri(VSMOD) Vref(VSMOD)
VSMOD = 0 VSMOD = -7%
0 -120 - 5.0
A A V
2002 Jun 24
20
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL fro(VSMOD) PARAMETER roll-off frequency (-3 dB) CONDITIONS Ii(VSMOD) = -60 A + 15 A 1 (RMS) - - - - - - - - - - -1.85 0.95 - - - - 0.76 0.54 0 - - MIN. -
TDA4841PS
TYP.
MAX. -
UNIT MHz
ADJUSTMENT OF VERTICAL POSITION; see Figs 3 to 7 VOFFS vertical position (referenced to 100% vertical size) register VOFFS = 0 register VOFFS = 15 register VOFFS = 8 VPOS vertical position (referenced to 100% vertical size) register VPOS = 0 register VPOS = 127 register VPOS = 64 ADJUSTMENT OF VERTICAL LINEARITY; see Figs 6 and 27 VLIN vertical linearity (S-correction) register VLIN = 0; control bit VSC = 0; note 8 register VLIN = 15; control bit VSC = 0; note 8 register VLIN = X; control bit VSC = 1; note 8 VLIN VLINBAL symmetry error of S-correction maximum VLIN ADJUSTMENT OF VERTICAL LINEARITY BALANCE; see Fig.7 vertical linearity balance (referenced to 100% vertical size) register VLINBAL = 0; note 8 register VLINBAL = 15; note 8 register VLINBAL = 8; note 8 VMOIRE modulation of vertical picture position by 12 vertical frequency (related to 100% vertical size) moire cancellation off IVOUT(nom)(p-p) Io(VOUT)(max) VVOUT E(offset)(max)(V) LEV(max) register VMOIRE = 0; control bit MOD = 0 register VMOIRE = 63; control bit MOD = 0 control bit MOD = 1 IVOUT = IVOUT1 - IVOUT2; nominal settings; note 8 control bit VOVSCN = 1 -1.40 1.40 0.08 0 0.03 0 -0.95 1.85 - - - - 0.94 0.66 4.2 2.5 1.5 % % % % % % 2 46 0 - - - - 0.7 % % % % -4 4 0.25 -11.5 11.5 0.09 - - - - - - % % % % % %
Vertical output stage: pin VOUT1 and VOUT2; see Fig.27 nominal differential output current (peak-to-peak value) maximum output current at pins VOUT1 and VOUT2 allowed voltage at outputs maximum offset error of vertical nominal settings; note 8 output currents maximum linearity error of vertical output currents nominal settings; note 8 0.85 0.6 - - - mA mA V % %
2002 Jun 24
21
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL EW drive output EW DRIVE OUTPUT STAGE: PIN EWDRV; see Figs 8 to 11 Vo(const)(EWDRV) bottom output voltage at pin EWDRV (internally stabilized) maximum output voltage load current temperature coefficient of output signal horizontal pincushion voltage register HPIN = 0; control bit VSC = 1; note 8 register HPIN = 0; register HTRAP = 32; register HSIZE = 255; control bit VSC = 1 note 9 1.05 1.2 PARAMETER CONDITIONS MIN.
TDA4841PS
TYP.
MAX.
UNIT
1.35
V
Vo(EWDRV)(max) IL(EWDRV) TCEWDRV VHPIN(EWDRV)
7.0 - - -
- - - 0.04 1.42 0.2 -0.64 0 0.2 -0.64 0 -0.5 0.5 -0.01 0.13 3.6 0.02 0.69 0 -120 - 5.0 -
- 2 600 - - - - - - - - - - - - - - - - - 500 - -
V mA 10-6/K V V V V V V V V V V V V V V V A A V MHz
register HPIN = 63; control - bit VSC = 1; note 8 VHCORT(EWDRV) horizontal corner correction voltage at top of picture register HCORT = 0; control bit VSC = 0; note 8 register HCORT = 63; control bit VSC = 0; note 8 register HCORT = X; control bit VSC = 1; note 8 VHCORB(EWDRV) horizontal corner correction voltage at bottom of picture register HCORB = 0; control bit VSC = 0; note 8 register HCORB = 63; control bit VSC = 0; note 8 register HCORB = X; control bit VSC = 1; note 8 VHTRAP(EWDRV) horizontal trapezium correction voltage register HTRAP = 63; note 8 register HTRAP = 32; note 8 VHSIZE(EWDRV) horizontal size voltage register HSIZE = 255; note 8 register HSIZE = 0; note 8 VHEHT(EWDRV) EHT compensation on horizontal size via HSMOD (pin 31) input current (pin 31) input resistance reference voltage at input roll-off frequency (-3 dB) Ii(HSMOD) = 0 Ii(HSMOD) = -60 A + 15 A (RMS) IHSMOD = 0; note 8 IHSMOD = -120 A; note 8 VHEHT = 0.02 V VHEHT = 0.69 V Ri(HSMOD) Vref(HSMOD) fro(HSMOD) - - - - - - -
register HTRAP = 0; note 8 - - - - - - - - 300 - 1
Ii(HSMOD)
2002 Jun 24
22
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS MIN. - 0.72
TDA4841PS
TYP.
MAX.
UNIT
TRACKING OF EWDRV OUTPUT SIGNAL WITH HORIZONTAL FREQUENCY PROPORTIONAL VOLTAGE fH(MULTI) VPAR(EWDRV) horizontal frequency range for tracking parabola amplitude at EWDRV (pin 11) IHREF = 1.052 mA; fH = 31.45 kHz; control bit FHMULT = 1; note 10 IHREF = 2.341 mA; fH = 70 kHz; control bit FHMULT = 1; note 10 function disabled; control bit FHMULT = 0; note 10 LEEWDRV linearity error of horizontal frequency tracking 15 - 80 - kHz V
-
1.42
-
V
- -
1.42 -
- 8
V %
Output for asymmetric EW corrections: pin ASCOR; see Figs 12 and 13 VHPARAL(ASCOR) vertical sawtooth voltage for EW parallelogram correction register HPARAL = 0; note 8 register HPARAL = 63; note 8 register HPARAL = 32; note 8 VHPINBAL(ASCOR) vertical parabola for pin unbalance correction register HPINBAL = 0; note 8 register HPINBAL = 63; note 8 register HPINBAL = 32; note 8 Vo(ASCOR)(max)(p-p) maximum output voltage swing (peak-to-peak value) Vo(ASCOR)(max) Vc(ASCOR) Vo(ASCOR)(min) Io(ASCOR)(max) Isink(ASCOR)(max) maximum output voltage centre voltage minimum output voltage maximum output current maximum output sink current Vo(ASCOR) 1.9 V Vo(ASCOR) 1.9 V - - - - - - - - - - - - -0.825 0.825 0.05 -1.0 1.0 0.05 4 6.5 4.0 1.9 -1.5 50 - - - - - - - - - - - - V V V V V V V V V V mA A
2002 Jun 24
23
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS - - - - 1.9 operation without pre-correction - - register HFOCUS = 0 register HFOCUS = 31 register VFOCUS = 0; note 8 register VFOCUS = 15; note 8 Vo(FOCUS)(max) Vo(FOCUS)(min) Io(FOCUS)(max) CL(FOCUS)(max) maximum output voltage minimum output voltage maximum output current maximum capacitive load Io(FOCUS) = 0 Io(FOCUS) = 0 - - - - 6.15 1.0 1.5 - MIN.
TDA4841PS
TYP.
MAX. - - - - - - 5.5 - - - - 6.65 1.6 - 20
UNIT
Focus section: pin FOCUS; see Figs 15 and 28 tprecor pre-correction of phase for horizontal focus parabola register HFOCAD = 0; see Fig.28 register HFOCAD = 1; see Fig.28 register HFOCAD = 2; see Fig.28 register HFOCAD = 3; see Fig.28 tW(hfb)(min) minimum width of horizontal flyback pulse maximum width of horizontal flyback pulse amplitude of horizontal focus parabola (peak-to-peak value) amplitude of vertical parabola (peak-to-peak value) 300 350 400 450 - 7.5 - 0.06 3.3 0.02 1.1 6.4 1.3 - - ns ns ns ns s s s V V V V V V mA pF
tW(hfb)(max) VHFOCUS(p-p) VVFOCUS(p-p)
B+ control section; see Figs 25 and 26 TRANSCONDUCTANCE AMPLIFIER: PINS BIN AND BOP Vi(BIN) Ii(BIN)(max) Vref(int) Vo(BOP)(min) Vo(BOP)(max) Io(BOP)(max) gm(OTA) Gv(ol) CBOP(min) input voltage maximum input current reference voltage at internal non-inverting input of OTA minimum output voltage maximum output voltage maximum output current transconductance of OTA open-loop voltage gain minimum value of capacitor at BOP (pin 3) note 11 note 12 Io(BOP) < 1 mA 0 - 2.37 - 5.0 - 30 - 10 - - 2.5 - 5.3 500 50 86 - 5.25 1 2.58 0.5 5.6 - 70 - - V A V V V A mS dB nF
2002 Jun 24
24
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS MIN. - - - - - - 250 500
TDA4841PS
TYP.
MAX.
UNIT
VOLTAGE COMPARATOR: PIN BSENS Vi(BSENS) Vi(BOP) ILI(BSENS)(max) Io(BDRV)(max) ILO(BDRV) Vsat(BDRV) toff(BDRV)(min) td(BDRV-HDRV) voltage range of positive comparator input voltage range of negative comparator input maximum leakage current discharge disabled 0 0 - 20 - - - - 5 5 -2 - 3 300 - - V V A mA A mV ns ns
OPEN-COLLECTOR OUTPUT STAGE: PIN BDRV maximum output current output leakage current saturation voltage minimum off-time delay between BDRV pulse and measured at HDRV pulse VHDRV = VBDRV = 3 V discharge stop level discharge current threshold voltage for restart minimum value of capacitor at BSENS (pin 4) capacitive load; IBSENS = 0.5 mA VBSENS > 2.5 V fault condition note 13 VBDRV = 16 V Io(BDRV) < 20 mA
BSENS DISCHARGE CIRCUIT: PIN BSENS VSTOP(BSENS) Idch(BSENS) Vth(BSENS)(restart) CBSENS(min) 0.85 4.5 1.2 2 1.0 6.0 1.3 - 1.15 7.5 1.4 - V mA V nF
Internal reference, supply voltage, soft start and protection VCC(stab) external supply voltage for complete stabilization of all internal references supply current standby supply current power supply rejection ratio of internal supply voltage supply voltage level for activation of continuous blanking minimum supply voltage level for function of continuous blanking supply voltage level for activation of HDRV, BDRV, VOUT1, VOUT2 and HUNLOCK supply voltage level for deactivation of BDRV, VOUT1, VOUT2 and HUNLOCK; also sets register SOFTST STDBY = 1; VPLL2 < 1 V; 3.5 V < VCC < 13.2 V f = 1 kHz VCC decreasing from 12 V 9.2 - 13.2 V
ICC ICC(stb) PSRR VCC(blank)
- - 50 8.2
68 9 - 8.6
- - - 9.0
mA mA dB V
VCC(blank)(min)
VCC decreasing from 12 V
2.5
3.5
4.0
V
Von(VCC)
VCC increasing from below typical 8.1 V
7.9
8.3
8.7
V
Voff(VCC)
VCC decreasing from above typical 8.3 V
7.7
8.1
8.5
V
2002 Jun 24
25
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SYMBOL PARAMETER CONDITIONS - - - - - - MIN.
TDA4841PS
TYP.
MAX. - - - - - -
UNIT
THRESHOLDS DERIVED FROM HPLL2 VOLTAGE VHPLL2(blank)(ul) VHPLL2(bduty)(ul) VHPLL2(bduty)(ll) VHPLL2(hduty)(ul) VHPLL2(hduty)(ll) VHPLL2(stby)(ll) upper limit for continuous blanking upper limit for variation of BDRV duty cycle lower limit for variation of BDRV duty cycle upper limit for variation of HDRV duty cycle lower limit for variation of HDRV duty cycle lower limit for VOUT1 and VOUT2 to be active via I2C-bus soft start upper limit for standby voltage lower limit for VOUT1 and VOUT2 to be active via external DC current 4.6 4.0 3.2 3.2 1.8 1.1 V V V V V V
VHPLL2(stby)(ul) VHPLL2(stby)(ll)
- -
1 0
- -
V V
Notes 1. For duration of vertical blanking pulse see "Vertical oscillator (oscillator frequency in application without adjustment of free-running frequency ffr(V))". 2. Continuous blanking at CLBL (pin 16) will be activated, if one of the following conditions is true: a) No horizontal flyback pulses at HFLB (pin 1) within a line b) X-ray protection is triggered c) Voltage at HPLL2 (pin 30) is low during soft start d) Supply voltage at VCC (pin 10) is low e) PLL1 unlocked while frequency-locked loop is in search mode. 3. Oscillator frequency is fmin when no sync input signal is present (no continuous blanking at pins 16 and 17). 4. Loading of HPLL1 (pin 26) is not allowed. 5. Voltage at HPLL1 (pin 26) is fed to HBUF (pin 27) via a buffer. Disturbances caused by horizontal sync are removed by an internal sample-and-hold circuit. 6. All vertical and EW adjustments according note 8, but VSIZE = 80% (register VSIZE = 63, VGAIN = 63 and control bit VOVSCN = 0). 7. Value of resistor at VREF (pin 23) may not be changed.
2002 Jun 24
26
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
8. All vertical and EW adjustments are specified at nominal vertical settings; unless otherwise specified, which means: a) VSIZE = 100% (register VSIZE = 127, VGAIN = 63 and control bit VOVSCN = 0) b) VSMOD = 0 (no EHT compensation) c) VPOS centred (register VPOS = 64) d) VLIN = 0 (register VLIN = X and control bit VSC = 1) e) VLINBAL = 0 (register VLINBAL = 8) f) FHMULT = 0 g) HPARAL = 0 (register HPARAL = 32) h) HPINBAL = 0 (register HPINBAL = 32) i) Vertical oscillator synchronized. 9. The output signal at EWDRV (pin 11) may consist of horizontal pincushion + corner correction + DC shift + trapezium correction. If the VOVSCN control bit is set, and the VPOS adjustment is set to an extreme value, the tip of the parabola may be clipped at the upper limit of the EWDRV output voltage range. The waveform of corner correction will clip if the vertical sawtooth adjustment exceeds 110% of the nominal setting. 10. If fH tracking is enabled, the amplitude of the complete EWDRV output signal (horizontal pincushion + corner correction + DC shift + trapezium) will be changed proportional to IHREF. The EWDRV low level of 1.2 V remains fixed. 11. First pole of transconductance amplifier is 5 MHz without external capacitor (will become the second pole, if the OTA operates as an integrator). V BOP 12. Open-loop gain is ------------- at f = 0 with no resistive load and CBOP = 10 nF [from BOP (pin 3) to GND]. V BIN 13. The recommended value for the pull-up resistor at pin 6 (BDRV) is 1 k.
2002 Jun 24
27
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Vertical and EW adjustments
TDA4841PS
handbook, halfpage
MBG590
IVOUT1
handbook, halfpage
MGS274
IVOUT1 IVOUT2
IVOUT2
l2
l1(1) I1(1) I2
t t (1) I1 is the maximum amplitude setting at register VSIZE = 127, register VGAIN = 63, control bit VOVSCN = 0. I 2 VSIZE = ------- x 100% I 1 I 2 VSMOD = ------- x 100% I 1 (1) I1 is the maximum amplitude setting at register VSIZE = 127, register VGAIN = 63, control bit VOVSCN = 0. I 2 VGAIN = ------- x 100% I 1
Fig.3 Adjustment of vertical size.
Fig.4 Adjustment of vertical size.
handbook, halfpage
MBG592
IVOUT1
handbook, halfpage
IVOUT1
MBG594
IVOUT2 l1(1) l2
IVOUT2
l2/t
l1(1)/t
t
t
(1) I1 is the maximum amplitude setting at register VSIZE = 127 and register VGAIN = 63. I 2 - I 1 VPOS = --------------------- x 100% 2 x I 1 I 2 - I 1 VOFFS = --------------------- x 100% 2 x I 1 (1) I1 is the maximum amplitude setting at register VSIZE = 127 and VLIN = 0%. I 1 - I 2 VLIN = --------------------- x 100% I 1
Fig.5 Adjustment of vertical position.
Fig.6 IVOUT1 and IVOUT2 as functions of time.
2002 Jun 24
28
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, halfpage
MGM068
handbook, halfpage
MGM069
IVOUT1 IVOUT2
VEWDRV
VHPIN(EWDRV) I2 I1(1)
t t
(1) I1 is the maximum amplitude setting at register VSIZE = 127 and register VOVSCN = 0. I 1 - I 2 VLINBAL = --------------------- x 100% 2 x I 1
Fig.8 Fig.7 IVOUT1 and IVOUT2 as functions of time.
Parabola amplitude at pin EWDRV as a function of time.
handbook, halfpage
MGM070
handbook, halfpage
MGM071
VEWDRV
VEWDRV VHCOR(EWDRV) VHTRAP(EWDRV)
t t
Fig.9 Influence of corner correction at pin EWDRV.
Fig.10 Influence of trapezium at pin EWDRV.
2002 Jun 24
29
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, halfpage
MGM072
handbook, halfpage
MGM073
VEWDRV
VASCOR
Vc(ASCOR) VHSIZE(EWDRV)
VHPARAL(ASCOR)
+
VHEHT(EWDRV)
t
t
Fig.11 Influence of HSIZE and EHT compensation at pin EWDRV.
Fig.12 Adjustment of parallelogram at pin ASCOR.
handbook, halfpage
MGM074
VASCOR
Vc(ASCOR)
VHPINBAL(ASCOR)
t
Fig.13 Adjustment of pin balance at pin ASCOR.
2002 Jun 24
30
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Pulse diagrams
TDA4841PS
handbook, full pagewidth
4.0 V automatic trigger level 3.8 V synchronized trigger level
vertical oscillator sawtooth at VCAP (pin 24)
1.4 V
vertical sync pulse
inhibited
internal trigger inhibit window (typical 4 ms) vertical blanking pulse at CLBL (pin 16) vertical blanking pulse at HUNLOCK (pin 17) IVOUT1 differential output currents VOUT1 (pin 13) and VOUT2 (pin 12) IVOUT2 7.0 V maximum
EW drive waveform at EWDRV (pin 11) DC shift 3.6 V maximum low-level 1.2 V fixed
MGM075
Fig.14 Pulse diagram for vertical part.
2002 Jun 24
31
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, full pagewidth
horizontal oscillator sawtooth at HCAP (pin 29)
horizontal sync pulse
PLL1 control current at HPLL1 (pin 26) video clamping pulse at CLBL (pin 16) triggered on trailing edge of horizontal sync
+
-
vertical blanking level
line flyback pulse at HFLB (pin 1)
PLL2 control current at HPLL2 (pin 30)
+
PLL2 control range
-
line drive pulse at HDRV (pin 8) 45 to 52% of line period
horizontal focus parabola at FOCUS (pin 32)
MGS275
Fig.15 Pulse diagram for horizontal part.
2002 Jun 24
32
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, full pagewidth
MGM077
relative tHDRV(OFF)/tH (%) 52
45 15 30 110 130 f (kHz) H
Fig.16 Relative tOFF time of HDRV as a function of horizontal frequency.
handbook, fullcomposite sync (TTL) pagewidth
at HSYNC (pin 15)
internal integration of composite sync
internal vertical trigger pulse
PLL1 control voltage at HPLL1 (pin 26) clamping and blanking pulses at CLBL (pin 16)
MGC947
a. Reduced influence of vertical sync on horizontal phase.
handbook, full pagewidth
composite sync (TTL) at HSYNC (pin 15)
clamping and blanking pulses at CLBL (pin 16)
MBG596
b. Generation of video clamping pulses during vertical sync with serration pulses.
Fig.17 Pulse diagrams for composite sync applications.
2002 Jun 24
33
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
I2C-BUS PROTOCOL Data format The format of data for the I2C-bus is given in Table 4. Table 4 S(1) Notes 1. S = START condition. 2. SLAVE ADDRESS (MAD) = 1000 1100. Data format SLAVE ADDRESS(2) A(3) SUBADDRESS(4) A(3)
TDA4841PS
DATA(5)
A(3)
P(6)
3. A = acknowledge, generated by the slave. No acknowledge is given, if the supply voltage is below 8.2 V for start-up and 8.0 V for shut-down procedure. 4. SUBADDRESS (SAD). 5. DATA byte. If more than 1 byte of DATA is transmitted, then no auto-increment of the significant subaddress is performed. 6. P = STOP condition. It should be noted that clock pulses according to the 400 kHz specification are accepted for 3.3 V and 5 V applications (reference level = 1.8 V). Default register values after power-up are random. All registers have to be preset via software before the soft start is enabled. It should be noted that if register contents are changed during the vertical scan, this might result in a visible interference on the screen. The cause for this interference is the abrupt change of picture geometry which takes effect at random locations within the visible picture. To avoid this kind of interference, at least the adjustment of some critical geometry parameters should be synchronized with the vertical flyback. The TDA4841PS offers a feature to synchronize any I2C-bus adjustment with the internal vertical flyback pulse. For this purpose the IC offers two different modes for the handling of I2C-bus data: * Direct mode * Buffered mode. Direct mode The direct mode is selected by setting the MSB of the I2C-bus register subaddress to logic 0. Any I2C-bus command is executed immediately after it was received, so the adjustment takes effect immediately after the end of I2C-bus transmission. This mode should be used if many register values have to be changed subsequently, i.e. during start-up, mode change, etc., and while there is no picture visible on the screen (blanked). The number of transmissions per V-period is not limited. Buffered mode The buffered mode is selected by setting the MSB of the I2C-bus register subaddress to logic 1. This mode is designed to avoid visible interferences on the screen during the I2C-bus adjustments. This mode should be used, if a single register has to be changed while the picture is visible, so i.e. for user adjustments. One received I2C-bus data byte is stored in an internal 8-bit buffer before it is passed to the DAC section. The first internal vertical blanking pulse (VBL) after end of transmission is used to synchronize the adjustment change with the vertical flyback. So the actual change of the picture size, position, geometry, etc. will take place during the vertical flyback period, and will thus be invisible. The IC gives acknowledge for chip address, subaddress and data of a buffered transmission. Only one I2C-bus transmission is accepted after each vertical blank. After one buffered transmission, the IC gives no acknowledge for further transmissions until next VBL pulse has occurred. The buffered mode is disabled while the IC is in standby mode.
2002 Jun 24
34
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
List of I2C-bus controlled switches
TDA4841PS
I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress: * SAD1 is the register subaddress to be used for transmissions in direct mode * SAD2 is the register subaddress to be used for transmissions in buffered mode. Table 5 Controlled switches; notes 1 and 2 FUNCTION 0: vertical, protection and horizontal unlock blanking available on pins CLBL and HUNLOCK 1: only vertical and protection blanking available on pins CLBL and HUNLOCK AGCDIS FHMULT 0: AGC in vertical oscillator active 1: AGC in vertical oscillator inhibited 0: EW output independent of horizontal frequency 1: EW output tracks with horizontal frequency VSC 0: VLIN, HCORT and HCORB adjustments enabled 1: VLIN, HCORT and HCORB adjustments forced to centre value MOD 0: horizontal and vertical moire cancellation enabled 1: horizontal and vertical moire cancellation disabled VOVSCN CLAMP VBLK ACD STDBY(3) SOFTST(3) 0: vertical size 100% 1: vertical size 116.8% for VGA350 0: trailing edge for horizontal clamp 1: leading edge for horizontal clamp 0: vertical blanking = 260 s 1: vertical blanking = 340 s 0: ASCOR disconnected from PLL2 1: ASCOR internally connected with PLL2 0: internal power supply enabled 1: internal power supply disabled 0: soft start not released (pin HPLL2 pulled to ground) 1: soft start is released (power-up via pin HPLL2) Notes 1. X = don't care. 2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred. 3. Bits STDBY and SOFTST can be reset by the internal protection circuit. 2002 Jun 24 35 1A 9A # X X X X X D1 # 1A 9A # X X X X X # D0 04 84 X D6 # # # # # # 09 89 D7 # # # # # # # 09 89 # D6 # # # # # # 0F 8F X D6 # # # # # # 08 88 D7 # # # # # # # 02 82 X D6 # # # # # # 0B 8B D7 # # # # # # # 0B 8B # D6 # # # # # # REGISTER ASSIGNMENT SAD1 SAD2 (HEX) (HEX) D7 D6 D5 D4 D3 D2 D1 D0 0A 8A X D6 # # # # # #
CONTROL BIT BLKDIS
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I2C-bus autosync deflection controller for PC monitors
I2C-bus data can be transmitted in direct or buffered mode and is defined by the MSB of the register subaddress: * SAD1 is the register subaddress to be used for transmissions in direct mode * SAD2 is the register subaddress to be used for transmissions in buffered mode. Table 6 Controlled functions; notes 1 and 2 NAME HSIZE HPOS HPIN BITS 8 8 6 REGISTER ASSIGNMENT SAD1 SAD2 CTRL (HEX) (HEX) D7 D6 D5 D4 D3 D2 D1 D0 BIT 01 07 0F 81 87 8F D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 X # D5 D4 D3 D2 D1 D0 - - - RANGE 0.1 to 3.6 V 13% of horizontal period 0 to 1.42 V - - VSIZE, VOVSCN, VPOS, HSIZE and HSMOD VSIZE, VOVSCN, VPOS, HSIZE and HSMOD VSIZE, VOVSCN, VPOS, HSIZE and HSMOD VSIZE, VOVSCN, VPOS, HSIZE and HSMOD VSIZE, VOVSCN and VPOS VSIZE, VOVSCN and VPOS VSMOD VSMOD - - VSIZE, VOVSCN, VPOS and VSMOD VSIZE, VOVSCN, VPOS and VSMOD FUNCTION TRACKS WITH
FUNCTION Horizontal size Horizontal position Horizontal pincushion
Horizontal trapezium correction Horizontal corner correction at top of picture Horizontal corner correction at bottom of picture Horizontal parallelogram EW pin balance Vertical size Vertical position Vertical gain Vertical offset Vertical linearity Vertical linearity balance
HTRAP
6
03
83
X
X
D5 D4 D3 D2 D1 D0
-
500 mV (p-p)
HCORT
6
04
84
X
#
D5 D4 D3 D2 D1 D0
VSC
+15 to -46% of parabola amplitude +15 to -46% of parabola amplitude 1.2% of horizontal period 1.2% of horizontal period 60 to 100% 11.5% 70 to 100% 4%
HCORB
6
02
82
X
#
D5 D4 D3 D2 D1 D0
VSC
HPARAL HPINBAL VSIZE VPOS VGAIN VOFFS VLIN VLINBAL
6 6 7 7 6 4 4 4
09 0B 08 0D 0A 0E 05 05
89 8B 88 8D 8A 8E 85 85
# # # X X #
# #
D5 D4 D3 D2 D1 D0 D5 D4 D3 D2 D1 D0
ACD ACD - -
D6 D5 D4 D3 D2 D1 D0 D6 D5 D4 D3 D2 D1 D0 # # D5 D4 D3 D2 D1 D0 # # D3 D2 D1 D0 # # # #
TDA4841PS
Product specification
D7 D6 D5 D4 # # # #
VSC -
-2 to -46% 1.4% of 100% vertical size
D3 D2 D1 D0
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I2C-bus autosync deflection controller for PC monitors
FUNCTION Moire cancellation via vertical position Moire cancellation via horizontal position Vertical focus Horizontal focus Horizontal focus pre-correction Notes 1. X = don't care.
NAME VMOIRE HMOIRE VFOCUS HFOCUS HFOCAD
BITS 6 6 4 5 2
RANGE
MOD 0 to 0.08% of vertical amplitude MOD 0.07% of horizontal period - - - 0 to 1.1 V 0 to 3.3 V 300 to 450 ns
D7 D6 D5 D4 # # X X
D4 D3 D2 D1 D0 # # # # #
D7 D6
2. # = this bit is occupied by another function. If the register is addressed, the bit values for both functions must be transferred.
TDA4841PS
Product specification
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Start-up procedure VCC < 8.3 V:
START
TDA4841PS
Power-down mode (XXXX XXXX) no acknowledge is given by IC all register contents are random VCC > 8.3 V Standby mode (XXXX XX01) STDBY = 1 SOFTST = 0 all other register contents are random
L1
* As long as the supply voltage is too low for correct operation, the IC will give no acknowledge due to internal Power-On Reset (POR) * Supply current is 9 mA or less. VCC > 8.3 V: * Internal POR has ended and the IC is in standby mode * Control bits STDBY and SOFTST are reset to their start values * All other register contents are random * Pin HUNLOCK is at HIGH-level. Setting control bit STDBY = 0: * Enables internal power supply * Supply current increases from 9 to 68 mA * When VCC < 8.6 V register SOFTST cannot be set by the I2C-bus * Output stages are disabled * Pin HUNLOCK is at HIGH-level. Setting all registers to defined values: * Due to the hardware configuration of the IC (no auto-increment) any register setting needs a complete 3-byte I2C-bus data transfer as follows: START - IC address - subaddress - data - STOP. Setting control bit SOFTST = 1: * Before enabling the soft-start sequence a delay of minimum 80 ms is necessary to obtain correct function of the horizontal drive * HDRV duty cycle increases * BDRV duty cycle increases * VOUT1 and VOUT2 are enabled * PLL1 and PLL2 are enabled. IC in full operation: * Pin HUNLOCK is at LOW-level when PLL1 is locked * Any change of the register content will result in an immediate change of the output behaviour * Setting control bit SOFTST = 0 is the only way (except power-down via pin VCC) to leave the operating mode.
MGL791
L2
S
8CH
A
1AH
A
00H
AP
Protection mode (XXXX XX00) STDBY = 0 SOFTST = 0 all other register contents are random
S
8CH
A
SAD
A
DATA
AP
Protection mode (XXXX XX00) STDBY = 0 SOFTST = 0 registers are pre-set
no
all registers defined? yes
S
8CH
A
1AH
A
02H
AP
L3
Soft-start sequence (XXXX XX10) STDBY = 0 SOFTST = 1
Operating mode (XXXX XX10) STDBY = 0 SOFTST = 1
no
change/refresh of data? yes
SOFTST = 0? yes
no
S
8CH
A
SAD
A
DATA
AP
L4 (1)
Soft-down sequence: * See L4 of Fig.19 for starting the soft-down sequence.
(1) See Fig.19.
Fig.18 I2C-bus flow for start-up.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Protection and standby mode
L4
TDA4841PS
Soft-down sequence: * Start the sequence by setting control bit SOFTST = 0
A 00H AP
S
8CH
A
1AH
* BDRV duty cycle decreases * HDRV duty cycle decreases. Protection mode: * Pins HDRV and BDRV are floating * Pins VOUT1 and VOUT2 are floating * Continuous blanking on pin CLBL is active * Pin HUNLOCK is floating * PLL1 and PLL2 are disabled * Register contents are kept in internal memory. Protection mode can be left by 3 ways:
Soft-down sequence (XXXX XX00) STDBY = 0 SOFTST = 0
Protection mode (XXXX XX00) STDBY = 0 SOFTST = 0 registers are set
no
STDBY = 1? yes
SOFTST = 1? yes L3 (1)
no
1. Entering standby mode by setting control bit SOFTST = 0 and bit STDBY = 1 2. Starting the soft-start sequence by setting control bit SOFTST = 1 (bit STDBY = don't care); see L3 of Fig.18 for continuation
S
8CH
A
1AH
A
01H
AP
3. Decreasing the supply voltage below 8.1 V. Standby mode: * Set control bit STDBY = 1 * Driver outputs are floating (same as protection mode) * Supply current is 9 mA * Only the I2C-bus section and protection circuits are operative * Contents of all registers are lost, except the value of bit STDBY and bit SOFTST * See L2 of Fig.18 for continuation.
Standby mode (XXXX XX01) STDBY = 1 SOFTST = 0 all other register contents are random
L2 (1) (1) See Fig.18.
MGL790
Fig.19 I2C-bus flow for standby mode and protection mode.
2002 Jun 24
39
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, full pagewidth
(ANY Mode) VCC < 8.1 V Power-Down Mode no acknowledge is given by IC all register contents are random VCC 8.6 V 8.1 V VCC 8.6 V 8.1 V
MGM079
a soft-down sequency followed by a soft start sequence is generated internally.
IC enters standby mode.
L1 (1)
(1) See Fig.18.
Fig.20 I2C-bus flow for any mode.
Power-down mode Power dip of VCC < 8.6 V: * The soft-down sequence is started first * Then the soft-start sequence is generated internally. Power dip of VCC < 8.1 V or VCC shut-down: * This function is independent from the operating mode, therefore it works under any condition * All driver outputs are immediately disabled * IC enters standby mode. Standby mode detection Execute data transmission twice to assure that there was no data transfer error.
S chip address 8CH A yes acknowledge was given on data? S chip address 8CH A Normal operation
I2C-bus transmission subaddress 0XH A data XXH A P
no I2C-bus transmission subaddress 0XH A data XXH A P
yes
acknowledge was given on data?
no Standby mode
MGS276
Fig.21 Possible standby mode detection.
2002 Jun 24
40
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Start-up and shut-down sequences
TDA4841PS
handbook, full pagewidth
MGM082
VCC
8.6 V continuous blanking off PLL2 soft start/soft-down enabled(1)
8.3 V
data accepted from I2C-bus video clamping pulse enabled if control bit STDBY = 0
3.5 V
continuous blanking (pin 16 and 17) activated
time
a. Start-up sequence.
handbook, full pagewidth
MGM083
VCC 8.6 V continuous blanking (pin 16 and 17) activated PLL2 soft-down sequence is triggered(2)
8.1 V
no data accepted from I2C-bus video clamping pulse disabled
3.5 V
continuous blanking disappears
time
b. Shut-down sequence.
(1) See Fig.23a. (2) See Fig.23b.
Fig.22 Activation of start-up and shut-down sequences via supply voltage.
2002 Jun 24
41
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Soft-start and soft-down sequences
TDA4841PS
handbook, full pagewidth
MHB495
VHPLL2 4.6 V continuous blanking off PLL2 enabled frequency detector enabled HDRV/HFLB protection enabled 4.0 V
ea se s
BDRV duty cycle has reached nominal value
cl e
in cr
du ty
cy
3.2 V
BDRV duty cycle begins to increase HDRV duty cycle has reached nominal value
1.8 V 1.0 V
HDRV duty cycle begins to increase
VOUT1 and VOUT2 enabled
time
a. Soft-start sequence for VCC > 8.6 V.
handbook, full pagewidth
MHB496
VHPLL2
4.6 V continuous blanking (pin 16 and 17) activated PLL2 disabled frequency detector disabled HDRV/HFLB protection disabled 4.0 V
du
BDRV duty cycle begins to decrease(1)
b. Soft-down sequence for VCC > 8.6 V.
(1) Pins HDRV and BDRV are floating for VCC < 8.6 V.
Fig.23 Activation of PLL2 soft-start and soft-down sequences via the I2C-bus.
ty cl cy e de ea cr se s
2.8 V
BDRV floating HDRV duty cycle begins to decrease(1) 1.8 V HDRV floating
1.0 V VOUT1 and VOUT2 floating
time
2002 Jun 24
42
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
handbook, full pagewidth
X-ray latch triggered
VXRAY
VHUNLOCK
BDRV duty cycle
floating
HDRV duty cycle
floating
VOUT1, VOUT2 approximately 25 ms
floating
MGM087
Fig.24 Activation of soft-down sequence via pin XRAY.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
APPLICATION INFORMATION
VCC VHPLL2 2 VHDRV 6 SOFT START S 2.5 V OTA R Q INVERTING BUFFER Q Vi R6(1) 3 VBDRV
TDA4841PS
handbook, full pagewidth
L D2
TR1
HORIZONTAL OUTPUT STAGE
DISCHARGE
1 horizontal flyback pulse
D1
5 VBIN R1
3 VBOP
4 R5 4 VBSENS C4
R4
MGM080
C1 R2 R3 C2 >10 nF CBOP
EWDRV For f < 50 kHz and C2 < 47 nF calculation formulas and behaviour of the OTA are the same as for an OP. An exception is the limited output current at BOP (pin 3). See Chapter "Characteristics", subheading "B+ control section; see Figs 25 and 26". (1) The recommended value for R6 is 1 k.
a. Feedback mode application.
handbook, full pagewidth
1 horizontal flyback pulse
2 VHDRV ton 3 VBDRV td(BDRV) VBSENS = VBOP 4 VBSENS
MBG600
toff(min) VRESTART(BSENS) VSTOP(BSENS)
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.25 Application and timing for feedback mode.
2002 Jun 24
44
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
TDA4841PS
VCC VHPLL2 2 VHDRV 6 SOFT START S 2.5 V OTA R Q 3 VBDRV Q INVERTING BUFFER R4(1)
horizontal flyback pulse 1
HORIZONTAL OUTPUT STAGE
EHT transformer
D2
DISCHARGE TR1
5 IMOSFET
5 EHT adjustment R1 VBIN D1 TR2 power-down C1 R2
3 VBOP
4
R3 4 VBSENS CBSENS >2 nF
MGM081
CBOP > 10 nF (1) The recommended value for R4 is 1 k.
a. Forward mode application.
handbook, full pagewidth 1 horizontal
flyback pulse
2 VHDRV ton 3 VBDRV td(BDRV) VBOP 4 VBSENS VBOP VRESTART(BSENS) VSTOP(BSENS) 5 IMOSFET
MBG602
toff
(discharge time of CBSENS)
b. Waveforms for normal operation.
c. Waveforms for fault condition.
Fig.26 Application and timing for feed forward mode.
2002 Jun 24
45
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Vertical linearity error
TDA4841PS
handbook, halfpage I
VOUT (A)
(1)
MBG551
+415
I1(2)
0
I2(3)
(1) (2) (3) (4)
IVOUT = IVOUT1 - IVOUT2. I1 = IVOUT at VVCAP = 1.9 V. I2 = IVOUT at VVCAP = 2.6 V. I3 = IVOUT at VVCAP = 3.3 V.
-415
I3(4) VVCAP
I1 - I3 Which means: I 0 = -------------2 I2 - I3 I1 - I2 Vertical linearity error = 1 - max -------------- or -------------- I0 I0
Fig.27 Definition of vertical linearity error.
H-focus pre-correction
handbook, halfpage
(1)
(2)
MGS282
(1) Line flyback pulse at HFLB (pin 1). (2) Horizontal focus parabola at FOCUS (pin 32).
t precor = 450 ns t precor = 300 ns
Fig.28 Definition of H-focus pre-correction.
2002 Jun 24
46
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
Printed-circuit board layout
TDA4841PS
handbook, full pagewidth
further connections to other components or ground paths are not allowed
external components of horizontal section 32 31 30 29 28 27 26 25 24 23
external components of vertical section 22 21 20 19 18 15 17 16
external components of horizontal section
pin 25 should be the 'star point' for all small signal components
no external ground tracks connected here
47 nF
2 nF
TDA4841PS
10 11 12 13 14
1
2
3
4
5
6
7
8
47 pF
100 F 12 V
9
B-drive line in parallel to ground
external components of driver stages
only this path may be connected to general ground of PCB SMD
MHB605
For optimum performance of the TDA4841PS the ground paths must be routed as shown. Only one connection to other grounds on the PCB is allowed. Note: The tracks for HDRV and BDRV should be kept separate.
Fig.29 Hints for Printed-Circuit Board (PCB) layout.
2002 Jun 24
47
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
INTERNAL PIN CONFIGURATION PIN 1 SYMBOL HFLB
1.5 k 1
TDA4841PS
INTERNAL CIRCUIT
7x
MBG561
2
XRAY
5 k 2
6.25 V
MBG562
3
BOP
3
5.3 V
MBG563
4
BSENS
4
MBG564
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 5 SYMBOL BIN
5
TDA4841PS
INTERNAL CIRCUIT
MBG565
6
BDRV
6
MBG566
7 8
PGND HDRV
power ground, connected to substrate
8
MGM089
9
XSEL
4 k 9
MBK381
10
VCC
10
MGM090
11
EWDRV
108 11 108
MBG570
2002 Jun 24
49
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 12 SYMBOL VOUT2 INTERNAL CIRCUIT
TDA4841PS
12
MBG571
13
VOUT1
13
MBG572
14
VSYNC
100 14 2 k 7.3 V 1.4 V
MBG573
15
HSYNC
1.28 V 85 15 7.3 V 1.4 V
MBG574
16
CLBL
16
MBG575
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 17 SYMBOL HUNLOCK INTERNAL CIRCUIT
TDA4841PS
17
MGM091
18
SCL
18
MGM092
19
SDA
19
MGM093
20
ASCOR
480
20
MGM094
21
VSMOD
250 21 5V
MGM095
2002 Jun 24
51
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 22 SYMBOL VAGC INTERNAL CIRCUIT
TDA4841PS
22
MBG581
23
VREF
23
3V
MBG582
24
VCAP
24
MBG583
25 26
SGND HPLL1
signal ground
26
4.3 V
MGM096
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 27 SYMBOL HBUF INTERNAL CIRCUIT
TDA4841PS
27
5V
MGM097
28 29
HREF HCAP
76 28 7.7 V 29
2.525 V
MBG585
30
HPLL2
7.7 V
30
HFLB
6.25 V
MGM098
2002 Jun 24
53
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PIN 31 SYMBOL HSMOD INTERNAL CIRCUIT
TDA4841PS
250 31 5V
MGM099
32
FOCUS
120 32 200 120
MGM100
Electrostatic discharge (ESD) protection
pin 7.3 V pin
MBG559
7.3 V
MBG560
Fig.30 ESD protection for pins 4, 11 to 13, 16 and 17.
Fig.31 ESD protection for pins 2, 3, 5, 18 to 24 and 26 to 32.
2002 Jun 24
54
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
PACKAGE OUTLINE SDIP32: plastic shrink dual in-line package; 32 leads (400 mil)
TDA4841PS
SOT232-1
D seating plane
ME
A2 A
L
A1 c Z e b 32 17 b1 wM (e 1) MH
pin 1 index E
1
16
0
5 scale
10 mm
DIMENSIONS (mm are the original dimensions) UNIT mm Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT232-1 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION A max. 4.7 A1 min. 0.51 A2 max. 3.8 b 1.3 0.8 b1 0.53 0.40 c 0.32 0.23 D (1) 29.4 28.5 E (1) 9.1 8.7 e 1.778 e1 10.16 L 3.2 2.8 ME 10.7 10.2 MH 12.2 10.5 w 0.18 Z (1) max. 1.6
ISSUE DATE 92-11-17 95-02-04
2002 Jun 24
55
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
SOLDERING Introduction to soldering through-hole mount packages This text gives a brief insight to wave, dip and manual soldering. A more in-depth account of soldering ICs can be found in our "Data Handbook IC26; Integrated Circuit Packages" (document order number 9398 652 90011). Wave soldering is the preferred method for mounting of through-hole mount IC packages on a printed-circuit board. Soldering by dipping or by solder wave The maximum permissible temperature of the solder is 260 C; solder at this temperature must not be in contact with the joints for more than 5 seconds.
TDA4841PS
The total contact time of successive solder waves must not exceed 5 seconds. The device may be mounted up to the seating plane, but the temperature of the plastic body must not exceed the specified maximum storage temperature (Tstg(max)). If the printed-circuit board has been pre-heated, forced cooling may be necessary immediately after soldering to keep the temperature within the permissible limit. Manual soldering Apply the soldering iron (24 V or less) to the lead(s) of the package, either below the seating plane or not more than 2 mm above it. If the temperature of the soldering iron bit is less than 300 C it may remain in contact for up to 10 seconds. If the bit temperature is between 300 and 400 C, contact may be up to 5 seconds.
Suitability of through-hole mount IC packages for dipping and wave soldering methods SOLDERING METHOD PACKAGE DIPPING DBS, DIP, HDIP, SDIP, SIL Note 1. For SDIP packages, the longitudinal axis must be parallel to the transport direction of the printed-circuit board. DATA SHEET STATUS DATA SHEET STATUS(1) Objective data PRODUCT STATUS(2) Development DEFINITIONS This data sheet contains data from the objective specification for product development. Philips Semiconductors reserves the right to change the specification in any manner without notice. This data sheet contains data from the preliminary specification. Supplementary data will be published at a later date. Philips Semiconductors reserves the right to change the specification without notice, in order to improve the design and supply the best possible product. This data sheet contains data from the product specification. Philips Semiconductors reserves the right to make changes at any time in order to improve the design, manufacturing and supply. Changes will be communicated according to the Customer Product/Process Change Notification (CPCN) procedure SNW-SQ-650A. suitable suitable(1) WAVE
Preliminary data
Qualification
Product data
Production
Notes 1. Please consult the most recently issued data sheet before initiating or completing a design. 2. The product status of the device(s) described in this data sheet may have changed since this data sheet was published. The latest information is available on the Internet at URL http://www.semiconductors.philips.com.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
DEFINITIONS Short-form specification The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 60134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification. PURCHASE OF PHILIPS I2C COMPONENTS DISCLAIMERS
TDA4841PS
Life support applications These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no licence or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified.
Purchase of Philips I2C components conveys a license under the Philips' I2C patent to use the components in the I2C system provided the system conforms to the I2C specification defined by Philips. This specification can be ordered using the code 9398 393 40011.
2002 Jun 24
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Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
NOTES
TDA4841PS
2002 Jun 24
58
Philips Semiconductors
Product specification
I2C-bus autosync deflection controller for PC monitors
NOTES
TDA4841PS
2002 Jun 24
59
Philips Semiconductors - a worldwide company
Contact information For additional information please visit http://www.semiconductors.philips.com. Fax: +31 40 27 24825 For sales offices addresses send e-mail to: sales.addresses@www.semiconductors.philips.com.
(c) Koninklijke Philips Electronics N.V. 2002
SCA74
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
753504/02/pp60
Date of release: 2002
Jun 24
Document order number:
9397 750 09802

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